1. Field of the Invention
This invention generally relates to an analog four quadrant multiplier using MOS integrated circuit technology, and more particularly relates to such an analog multiplier based on the quarter-square algebraic identity and utilizing low-gain differential summer and differential squaring circuits.
The multiplier of this invention, including theoretical analysis, simulations experimental test results are disclosed in detail in a doctoral thesis by PenaFinol, "Analog Four-Quadrant Multiplier Using NMOS Integrated Circuit Technology," presented to the Georgia Institute of Technology on June 4, 1982. The subject matter of this thesis is incorporated by reference herein.
2. Description of the Prior Art
There are several prior art methods used to perform analog multiplcation, namely electromechanical, magnetic (magnetoresistance, Hall effect), time-division, triangle averaging, log/antilog, quarter-square, variable transconductance and those based on A/D and D/A conversion techniques. Of these techniques, only the quarter-square and variable transconductance techniques having bandwidths above 1 MHz as does the invention disclosed herein. The quarter-square is the more accurate method. The variable transconductance has a larger bandwidth, but the quarter-square possesses one-half an order of magnitude more accuracy, typically 0.25%. At the present time, the 0.25% accuracy is obtained only through the use of expensive discrete circuitry. The design of a monolithic quarter-square multiplier with comparable or better accuracy to bandwidth ratio, would represent a significant contribution in the area of analog signal processing.
Traditionally, these multipliers have been implemented using bipolar technology. This technology has been the dominant one in the analog domain. Higher levels of monolithic integration are combining analog and digital circuits on the same MOS/LSI chip. Currently, analog integrated circuits are being fabricated using the same MOS technology employed in the realization of digital circuits.
The conventional method of performing the multiplication function based on the variable transconductance technique so far has been the only one which has been integrated in monolithic form. This method uses the inherent close matching and variable transconductance of bipolar junction transistor monolithic differential amplifiers. The circuit configuration for this method is the well-known Gilbert multiplier cell indicated in FIG. 1. The principle of operation of this circuit is briefly next explained.
FIG. 1 illustrates a conventional multiplier provided with a non-linearity cancellation circuit. This is the basic circuit utilized in commercially available transconductance multipliers such as the Motorola MC1595. It can be shown that the output is given by, EQU V.sub.o =[2R.sub.L /I.sub.o R.sub.1 R.sub.2 ]V.sub.1 V.sub.2. (1)
Equation (1) is obtained from the linear conversion of the input voltages to differential currents I.sub.1 and I.sub.2 provided by the emitter degeneration resistors R.sub.1 and R.sub.2 (I.sub.1 *.perspectiveto.V.sub.1 /R.sub.1 and I.sub.2 *.perspectiveto.V.sub.2 /R.sub.2), and to the linear ratios of the collector currents given by, EQU I.sub.2 /I.sub.1 =I.sub.6 /I.sub.8 =I.sub.5 /I.sub.7. (2)
Equation (2) is obtained assuming perfectly matching transistors and resistors and infinite common emitter current gain (.beta.) of the transistors. Thus, monolithic integrated circuit technology should be used in the fabrication of the variable transconductance multiplier. However, a small but finite mismatching will exist in the emitter areas, ohmic resistances, and .beta.'s.
This mismatch introduces nonlinearities and offset voltages and ultimately limits the accuracy of this compensated variable transconductance multiplier. Improved processing of device matching and laser trimming thin film resistors has produced high accuracies of about 1%. However, the extra processing steps increase considerably the cost.
The bandwidth for the multiplier shown in FIG. 1 is dominated by the equivalent input capacitance (Miller capacitance) of the bipolar transistors. Ten megahertz is a typical value for the maximum bandwidth of this type of multiplier. FIG. 1 illustrates the multiplier cell disclosed by Gilbert, B., "A Precise Four-Quadrant Multiplier with Subnanosecond Response," IEEE J. Solid-State Circuits, Vol. SC-3, pp. 365-373, Dec. 1968, and Gilbert, B., "A New Wide-Band Amplifier Technique," IEEE J. Solid-State Circuits, Vol. SC-3, pp. 353-365, Dec. 1968.
The basic Gilbert cell using NMOS devices is shown in FIG. 2. It can be shown that the output voltage is given by ##EQU1## where W and L are the gate width and length respectively, W/L is the resulting aspect ratio, and K.sub.P is a dimensional constant defined by ##EQU2## where .mu. is the effective bulk mobility of carriers (electrons), C.sub.ox is the gate oxide capacitance per unit oxide area, .epsilon..sub.ox is the oxide dielectric constant, and t.sub.ox is the oxide thickness. Equation ( 3) is valid under small-signal conditions provided that, EQU [K.sub.P (W/L).sub.1 V.sub.2.sup.2 ]/4I.sub.o &lt;&lt;1; and (5) EQU [K.sub.P (W/L).sub.2 V.sub.1.sup.2 ]/2I.sub.o &lt;&lt;1. (6)
Because of these small-signal level constraints, the useful range for good linearity is severely limited. A nonlinear cancellation approach similar to that used for the bipolar multiplier in FIG. 1 is not suitable in the FIG. 2 multiplier because of the different type of nonlinearity associated with MOSFETs. MOSFETs have a square law current-voltage dependency while bipolar junction transistors (BJTs) have an exponential relationship. Another shortcoming associated with the FIG. 2 NMOS multiplier is that large values of transconductance are required for proper operation of the circuit. The transconductance of a MOS transistor operating in the saturation region is derived as, ##EQU3## where I.sub.D is the drain current. Thus, in order to significantly increase the transconductance of the MOS devices, the aspect ratio (W/L) will have to be greatly increased as well as the drain current, I.sub.D. However, increasing these two variables causes new problems. For a transconductance of about 10m.OMEGA..sup.-1 (typical values for BJTs are in the 100m.OMEGA.-1 range) at 0.1 mA drain current, an aspect ratio of about 25,000 will be required. This is extremely large and impractical. An increase in channel width, W, means higher values of parasitic capacitances because of the larger areas which lowers the frequency response. Because of second-order effects associated with short-channel devices, the value of L cannot be decreased arbitrarily. An increase of I.sub.D, on the other hand, means higher power consumption. Thus, it can be expected that the overall performance of the NMOS variable transconductance multiplier will be inferior to that of the bipolar circuit.